In the field of electronic component design, engineers use simulation tools on a regular basis to test their designs. With such tools, engineers are able to detect and correct errors, and enhance the functionality of their designs without actually building a physical component. This leads to great savings in manufacturing and design costs. Over the years, a number of techniques and tools have been developed to aid in the simulation process.
Currently, simulation tools can simulate and test the behavior of a component design on several different levels. One level at which designs can be simulated is the transistor level. To test a design at this level, an engineer typically specifies a design using a transistor level description language, such as SPICE or SPECTRE. The design is then run through a transistor level simulation tool. Based upon the results of the simulation, the engineer can determine whether the design operated properly. While simulating a design at the transistor level is effective, it is often not the most efficient way to test a design. This is because transistor level simulation is relatively slow and quite resource intensive, and because designers often are not interested in the operation of a design at that low a level. As a result, it is often preferable to simulate the operation of a design at a higher logic level rather than at the transistor level.
To test a design at the logic level, a logic level representation of the design is needed. A logic level representation may be derived by submitting the transistor level description of the design to an abstraction mechanism, and having the abstraction mechanism generate an equivalent logic level description. The logic level description may be in a higher level description language such as Verilog HDL. In generating the logic level description, the abstraction mechanism analyzes various combinations of transistors and circuit elements in the transistor level description of the design, and transforms the combinations into elements that perform logic functions (e.g. AND, OR, etc.). By abstracting the functions performed by various transistors and circuit elements, the abstraction mechanism generates a higher level representation of the design, which is simpler and more efficient to simulate. Once derived, the logic level representation may be submitted to an event level simulator for simulation.
Currently, three basic approaches are used to perform functional abstraction on a transistor level representation. These include pattern matching, transformation rules, and symbolic analysis. With pattern matching, a user specifies to the abstraction mechanism a set of transistor level patterns. The abstraction mechanism then performs the abstraction by looking for all instances of those patterns in the transistor level representation. With transformation rules, the user specifies a set of rules for transforming or replacing portions of a transistor level representation with certain logic gates. Using these rules, the abstraction mechanism makes the specified transformations throughout the transistor level representation. A major issue with these approaches is that they both require the user to provide a complete set of patterns or transformation rules. As a result, their application is somewhat limited to abstraction of structured designs in which only a limited set of transistor level configurations are used.
The third approach, symbolic analysis, is an algorithmic technique that abstracts functionality based upon transistor sizes and connectivity. Given a transistor level representation, symbolic analysis generates a functionally equivalent logic level representation using logic primitives and explicit delays (previous state is modeled with an explicit delay). An advantage of symbolic analysis is that it does not require users to specify patterns or transformation rules. Thus, it performs abstraction “automatically”. A disadvantage of symbolic analysis is that it outputs a logic level representation that can only be submitted to an event level simulator for simulation. The output of symbolic analysis cannot be submitted to a cycle simulator, or an equivalence checker because it is not a cycle ready model. Symbolic analysis is described in detail in R. E. Bryant, “Extraction of Gate Level Models from Transistor Circuits by Four-Valued Symbolic Analysis,” International Conference on Computer Aided Design, 1991, pages 350-353, and in R. E. Bryant, “Boolean Analysis of MOS circuits,” IEEE Transactions on Computer Aided Design, Jul. 1987, pages 634-649. Both of these references are incorporated herein in their entirety by reference.
Overall, the abstraction techniques currently used are relatively rudimentary. They provide some capability for functionally abstracting simple elements, but they do not enable more complex structures, such as precharged latches and flip-flops to be abstracted (at least not to the latch or flip flop level). Because such structures are quite prevalent in modern component design, such an abstraction capability is needed.